The invention relates to integrated circuit devices, and more particularly to the compensation for performance variations in a transistor array.
In traditional integrated circuit design, a designer could count on the performance characteristics of a MOSFET gate as being determined by the width and length of the channel.
Here it should be clearly understood that “performance characteristics” as used herein corresponds to the general understanding of that term by those in the art. Specifically, that term comprehends both the drive current and threshold voltage of a MOSFET under design.
With the advent of sub-100 nm feature sizes, coupled with techniques such as strain engineering (as seen in U.S. patent application Ser. No. 11/291,294, entitled “Analysis of Stress Impact on Transistor Performance”, filed 1 Dec. 2005, owned by the assignee hereof and hereby incorporated herein), it has been found that additional variations occur, caused by the proximity of neighboring elements in the integrated circuit array, such as other MOSFET elements, contacts and the like.
Current design techniques cannot cope with such variations in an efficient manner. Normally, designers operate by simulation to lay out a MOSFET integrated circuit, and the first knowledge of unexpected variations generally is the failure of the actual circuit, after the prototypes are fabricated in silicon. That situation requires expensive and time-consuming redesign efforts. The art has thus created an opportunity to achieve more convenient and efficient designs by providing methods and systems for addressing the issue of process-induced variations.